5nm silicon chip
IBM developed the world’s first 5nm silicon chip in conjunction with Samsung and GlobalFoundries. The new chip is around the size of a fingernail, but is able to house up to 30 billion switches.
The development comes less than two years after IBM researchers made a 7-nanometer test node chip with 20 billion transistors.
The new design could be used in data-intensive applications related to the IoT and cognitive computing, among others.
IBM also claims that its capacity for reduced power consumption could mean that the batteries in smartphones and other devices could last two to three times as long on a single charge.
Mukesh Khare, vice-president of semiconductor technology research at IBM Research, said, the 5-nanometer chip could perform about 40 percent faster than a 10-nanometer chip. The chip could be 75 percent more power efficient.
The new chip is a brand-new architecture, avoid the current FinFET design.
IBM Research has apparently been looking into nanosheet semiconductor technology for over a decade. Right now, the most-advanced semiconductor chips used in a FinFET process with circuitry that is 10 nanometers in width.
FinFET is used to carry an electrical current. However, nanosheet transistors can use extreme ultraviolet lithography for precise size adjustments. Which allows the performance and power to be tailored for individual circuits.
According to IBM, FinFET chips can scale down to 5nm, but the denser transistors on that architecture doesn’t boost performance because the closer fins don’t provide more current flow.
IBM is presenting details of its research at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan.